View UDA1341TS_3050613.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product specification supersedes data of 2001 jun 29 2002 may 16 integrated circuits UDA1341TS economy audio codec for minidisc (md) home stereo and portable applications
2002 may 16 2 nxp semiconductors product specification economy audio codec for minidisc (md) home stereo and portable applications UDA1341TS contents 1 features 1.1 general 1.2 multiple format data interface 1.3 dac digital sound processing 1.4 advanced audio configuration 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 system clock 7.2 pin compatibility 7.3 analog front end 7.4 programmable gain amplifier (pga) 7.5 analog-to-digital converter (adc) 7.6 digital automatic gain control (agc) 7.7 agc status detection 7.8 digital mixer 7.9 decimation filter (adc) 7.10 overload detection (adc) 7.11 mute (adc) 7.12 interpolation filter (dac) 7.13 peak detector 7.14 quick mute 7.15 noise shaper (dac) 7.16 filter stream digital-to-analog converter (fsdac) 7.17 multiple format in put/output interface 7.18 l3-interface 7.19 address mode 7.20 data transfer mode 7.21 programming the sound processing and other features 7.21.1 status control 7.21.2 data0 direct control 7.21.3 data0 extended programming registers 7.21.4 data1 control 8 limiting values 9 thermal characteristics 10 dc characteristics 11 ac characteristics (analog) 12 ac characteristics (digital) 13 application information 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic pa ckages for wave and reflow soldering methods 16 data sheet status 17 disclaimers
2002 may 16 3 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 1 features 1.1 general ? low power consumption ? 3.0 v power supply ? 256f s , 384f s or 512f s system clock frequencies (f sys ) ? small package size (ssop28) ? partially pin compatible with uda1340m and uda1344ts ? fully integrated analog front end including digital agc ? adc plus integrated high-pass filter to cancel dc offset ? adc supports 2 v (rms value) input signals ? overload detector for easy record level control ? separate power control for adc and dac ? no analog post filter required for dac ? easy application ? functions controllable via l3-interface. 1.2 multiple format data interface ? i 2 s-bus, msb-justified and lsb-justified format compatible ? three combinational data formats with msb data output and lsb 16, 18 or 20 bits data input ? 1f s input and output format data rate. 1.3 dac digital sound processing ? digital db-linear volume co ntrol (low microcontroller load) ? digital tone control, bass boost and treble ? digital de-emphasis for 32, 44.1 or 48 khz audio sample frequencies (f s ) ? soft mute. 1.4 advanced audio configuration ? dac and adc polarity control ? two channel stereo single-ended input configuration ? microphone input with on-board pga ? optional differential input configuration for enhanced adc sound quality ? stereo line output (under microcontroller volume control) ? digital peak level detection ? high linearity, dynamic range and low distortion. 2 general description the UDA1341TS is a single-chip stereo analog-to-digital converter (adc) and digital-to-analog converter (dac) with signal processing features employing bitstream conversion techniques. its fully integrated analog front end, including programmable gain amplifier (pga) and a digital automatic gain control (agc). digital sound processing (dsp) featuring makes the device an excellent choice for primary home stereo minidisc applications, but by virtue of its low power and low voltage characteristics it is also suitable for portable applications such as md/cd boomboxes, notebook pcs and digital video cameras. the UDA1341TS is similar to the uda1340m and the uda1344ts but adds features such as digital mixing of two input signals and one channel with a pga and a digital agc. the UDA1341TS supports the i 2 s-bus data format with word lengths of up to 20 bits, the msb-justified data format with word lengths of up to 20 bits, the lsb-justified serial data format with word lengths of 16, 18 and 20 bits and three combinations of msb data output combined with lsb 16, 18 and 20 bits data input. the UDA1341TS has dsp features in playback mode like de-emphasis, volume, bass boost, treble and soft mute, which can be controlled via the l3-interface with a microcontroller. 3 ordering information type number package name description version UDA1341TS ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1
2002 may 16 4 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 4 quick reference data notes 1. the adc inputs can be used in a 2 v (rms value) input signal configuration when a resistor of 12 k is used in series with the inputs and 1 or 2 v (rms value) input signal operation can be selected via the input gain switch (igs). 2. the adc input signal scales inversely proportional with the power supply voltage. 3. the dac output voltage scales linear with the dac analog supply voltage. symbol parameter conditions min. typ. max. unit supplies v dda(adc) adc analog supply voltage 2.4 3.0 3.6 v v dda(dac) dac analog supply voltage 2.4 3.0 3.6 v v ddd digital supply voltage 2.4 3.0 3.6 v i dda(adc) adc analog supply current operation mode ? 12.5 ? ma adc power-down ? 6.0 ? ma i dda(dac) dac analog supply current operation mode ? 7.0 ? ma dac power-down ? 50 ? a i ddd digital supply current operation mode ? 7.0 ? ma t amb operating ambient temperature ? 20 ? +85 c analog-to-digital converter v i(rms) input voltage (rms value) notes 1 and 2 ? 1.0 ? v (thd + n)/s total harmonic distortion-plus-noise to signal ratio stand-alone mode 0db ?? 85 ? 80 db ? 60 db; a-weighted ?? 37 ? 33 db double differential mode 0db ?? 90 ? 85 db ? 60 db; a-weighted ?? 40 ? 36 db s/n signal-to-noise ratio v i = 0 v; a-weighted stand-alone mode ? 97 ? db double differential mode ? 100 ? db cs channel separation ? 100 ? db programmable gain amplifier (thd + n)/s total harmonic distortion-plus-noise to signal ratio 1khz; f s = 44.1 khz 0db ?? 85 ? db ? 60 db; a-weighted ?? 37 ? db s/n signal-to-noise ratio v i = 0 v; a-weighted ? 95 ? db digital-to-analog converter v o(rms) output voltage (rms value) supply voltage = 3 v; note 3 ? 900 ? mv (thd+n)/s total harmonic distortion-plus-noise to signal ratio 0db ?? 91 ? 86 db ? 60 db; a-weighted ?? 40 ? db s/n signal-to-noise ratio code = 0; a-weighted ? 100 ? db cs channel separation ? 100 ? db
2002 may 16 5 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 5 block diagram fig.1 block diagram. handbook, full pagewidth mgr427 adc2 pga pga 6 8 18 16 17 19 25 12 15 14 13 9 vinl2 v ssd v ddd datao bck ws datai voutl 27 24 26 voutr sysclk l3data l3clock l3mode overfl vinr2 10 11 decimation filter digital mixer digital agc digital interface l3-bus interface peak detector adc2 dac v ssa(dac) v dda(dac) dac interpolation filter noise shaper dsp features 20 test1 21 test2 31 v dda(adc) v ssa(adc) 75 v adcp v adcn UDA1341TS 22 agcstat 23 qmute 28 v ref adc1 0 db/6 db switch 0 db/6 db switch 2 4 vinl1 vinr1 adc1
2002 may 16 6 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 6 pinning symbol pin description v ssa(adc) 1 adc analog ground vinl1 2 adc1 input left v dda(adc) 3 adc analog supply voltage vinr1 4 adc1 input right v adcn 5 adc negative reference voltage vinl2 6 adc2 input left v adcp 7 adc positive reference voltage vinr2 8 adc2 input right overfl 9 decimation filter overflow output v ddd 10 digital supply voltage v ssd 11 digital ground sysclk 12 system clock 256f s , 384f s or 512f s l3mode 13 l3-bus mode input l3clock 14 l3-bus clock input l3data 15 l3-bus data input and output bck 16 bit clock input ws 17 word select input datao 18 data output datai 19 data input test1 20 test control 1 (pull-down) test2 21 test control 2 (pull-down) agcstat 22 agc status qmute 23 quick mute input voutr 24 dac output right v dda(dac) 25 dac analog supply voltage voutl 26 dac output left v ssa(dac) 27 dac analog ground v ref 28 adc and dac reference voltage symbol pin description fig.2 pin configuration. handbook, halfpage v ssa(adc) vinl1 v dda(adc) vinr1 v adcn vinl2 v adcp vinr2 overfl v ddd v ssd sysclk l3mode l3clock v ref v ssa(dac) voutl v dda(dac) qmute agcstat voutr test2 test1 datai datao ws bck l3data 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 UDA1341TS mgr428 fig.3 compatible pins with uda1340m. handbook, halfpage v ssa(adc) vinl1 v dda(adc) vinr1 v adcn vinl2 v adcp vinr2 overfl v ddd v ssd sysclk l3mode l3clock v ref v ssa(dac) voutl v dda(dac) qmute agcstat voutr test2 test1 datai datao ws bck l3data marked pins are compatible with uda1340m 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 UDA1341TS mgr429
2002 may 16 7 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7 functional description 7.1 system clock the UDA1341TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. the system frequency is selectable. the options are 256f s , 384f s or 512f s . the system clock must be locked in frequency to the digital interface signals. 7.2 pin compatibility the UDA1341TS is partially pin compatible with the uda1340m and uda1344ts, making an upgrade of a printed-circuit board from uda1340m to UDA1341TS easier. the pins that are compatible with the uda1340m are marked in fig.3. 7.3 analog front end the analog front end of the UDA1341TS consists of two stereo adcs with a programmable gain amplifier (pga) in channel 2. the pga is intended to pre-amplify a microphone signal applied to the input channel 2. input channel 1 has a selectable 0 or 6 db gain stage, to be controlled via the l3-interface. in this way, input signals of 1 v (rms value) or 2 v (rms value) e.g. from a cd source can be supported using an external resistor of 12 k in series with the input channel 1. the application modes are given in table 1. table 1 application modes using input gain stage note 1. if there is no need for 2 v (rms value) input signal support, the external resistor should not be used. 7.4 programmable gain amplifier (pga) the pga can be set via the l3-interface at the gain settings: ? 3, 0, 3, 9, 15, 21 or 27 db. 7.5 analog-to-digit al converter (adc) the stereo adc of the UDA1341TS consists of two 3rd-order sigma-delta modulators. they have a modified ritchie-coder architecture in a differential switched capacitor implementation. the over-sampling ratio is 128. 7.6 digital automatic gain control (agc) input channel 2 has a digital agc to compress the dynamic range when a microphone signal is applied to input channel 2. the digital agc can be switched on and off via the l3-interface. in the on state the agc compresses the dynamic range of the input signal of input channel 2. via the l3-interface the user can set the parameters of the agc: attack time, decay time and output level. when the agc is set off via the l3-interface, the gain of input channel 2 can be set manually. in this case the gain of the pga and digital agc are combined. the range of the gain of the input channel 2 is from ? 3to+60.5db in steps of 0.5 db. 7.7 agc status detection the agcstat signal from the digital agc is high when the gain level of the agc is be low 8 db. this signal can be used to give the pga a new gain setting via the l3-interface and to power e.g. a led. 7.8 digital mixer the two stereo adcs (including the agc) can be used in four modes: ? adc1 only mode (for line input); input channel 2 is off ? adc2 only mode, including pga and digital agc (for microphone input); input channel 1 is off ? adc1 + adc2 mixer mode, including pga and agc ? adc1 and adc2 double differential mode (improved adc performance). important : in order to prevent crosstalk between the line inputs no signal should be applied to the microphone input in the double differential mode. in all modes (except the double differential mode) a reference voltage is always present at the input of the adc. however, in the double differential mode there is no reference voltage present at the microphone input. in the mixer mode, the output signals of both adcs in channel 1 and channel 2 (after the digital agc) can be mixed with coefficients that ca n be set via the l3-interface. the range of the mixer coefficients is from 0 to ? db in 1.5 db steps. resistor (12 k ) input gain switch maximum input voltage present 0 db 2 v (rms value) input signal; note 1 present 6 db 1 v (rms value) input signal absent 0 db 1 v (rms value) input signal absent 6 db 0.5 v (rms value) input signal
2002 may 16 8 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.9 decimation filter (adc) the decimation from 128f s is performed in two stages. the first stage realizes 3rd order characteristic, decimating by 16. the second stage consists of 3 half-band filters, each decimating by a factor of 2. table 2 decimation filter characteristics 7.10 overload detection (adc) this name is convenient but a little inaccurate . in practice the output is used to indicate whenever that output data, in either the left or right channel, is bigger than ? 1db (actual figure is ? 1.16 db) of the maximum possible digital swing. if this condition is detected the overfl output is forced high for at least 512f s cycles (11.6 ms at f s =44.1khz). this time-out is reset for each infringement. 7.11 mute (adc) on recovery from power-down or switching on of the system clock, the serial data output on pin datao is held at low level until valid data is available from the decimation filter. this time depends on whether the dc-cancellation filt er is selected: ? dc cancel off: ; t = 23.2 ms at f s =44.1khz ? dc cancel on: ; t = 279 ms at f s =44.1khz. 7.12 interpolation filter (dac) the digital filter interpolates from 1f s to 128f s by means of a cascade of a recursive filter and a finite impulse response (fir) filter. table 3 interpolation filter characteristics 7.13 peak detector in the playback path a peak level detector is build in. the position of the peak detection can be set via the l3-interface to either before or after the sound features. the peak level detector is implemented as a peak-hold detector, which means that the highest sound level is hold until the peak level is read out via the l3-interface. after read-out the peak level registers are reset. 7.14 quick mute a hard mute can be activated via the static pin qmute. when qmute is set high, the output signal is instantly muted to zero. setting qmut e to low, the mute is instantly de-activated. 7.15 noise shaper (dac) the 3rd-order noise shaper operates at 128f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique allows for high signal-to-noise ratios. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. item conditions value (db) passband ripple 0 to 0.45f s 0.05 stop band >0.55f s ? 60 dynamic range 0 to 0.45f s 108 overall gain input channel 1; 0 db input ? 1.16 sin x x ----------- - t 1024 f s ------------ - = t 12288 f s ---------------- = item conditions value (db) passband ripple 0 to 0.45f s 0.03 stop band >0.55f s ? 50 dynamic range 0 to 0.45f s 108
2002 may 16 9 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.16 filter stream digi tal-to-analog converter (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output curr ent to an output voltage signal capable of driving a line output. 7.17 multiple format input/output interface the UDA1341TS supports the following data formats: ? i 2 s-bus with word length up to 20 bits ? msb-justified serial format with word length up to 20 bits ? lsb-justified serial format with word length of 16, 18 or 20 bits ? msb data output with lsb 16, 18 or 20 bits input. left and right data-channel words are time multiplexed. the formats are illustrated in fig.4. the UDA1341TS allows for double speed data monitoring purposes. in this case the sound features bass boost, treble and de-emphasis cannot be used. however, volume control and soft-mute can still be controlled. the double speed monitoring option can be set via the l3-interface. the bit clock frequency must be 64 times word select frequency or less, so f bck 64 f ws .
2002 may 16 10 nxp semiconductors product specification economy audio codec for minidisc (md) home stereo and portable applications UDA1341TS han dbook, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits msb-justified format ws left left left left right right right right 3 2 2 2 15 16 17 18 1 15 16 1 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 > =8 > =8 bck d ata ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 > =8 > =8 bck d ata ws bck d ata ws bck d ata ws bck d ata input format i 2 s-bus mgg84 1 fig.4 serial interface formats.
2002 may 16 11 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.18 l3-interface the UDA1341TS has a microcontroller input mode. in the microcontroller mode, all the digital sound processing features and the system co ntrolling featur es can be controlled by the microcontroller. the controllable features are: ? reset ? system clock frequency ? power control ? dac gain switch ? adc input gain switch ? adc/dac polarity control ? double speed playback ? de-emphasis ? volume ? mode switch ? bass boost ? treble ? mute ? mic sensitivity control ? agc control ? input amplifier gain control ? digital mixer control ? peak detection position. via the l3-interface the peak level value of the signal in the dac path can be read out from the UDA1341TS to the microcontroller. the exchange of data and control information between the microcontroller and the UDA1341TS is accomplished through a serial hardware l3-interface comprising the following pins: ? l3data: microcontroller interface data line ? l3mode: microcontroller interface mode line ? l3clock: microcontroller interface clock line. information transfer through the microcontroller bus is organized in accordance with the so called ?l3? format, in which two different modes of operation can be distinguished: address mode and data transfer mode. the address mode is required to select a device communicating via the l3-bus and to define the destination registers for the data transfer mode. data transfer can be in bo th directions: input to the UDA1341TS to program its sound processing and system controlling features and outpu t from the UDA1341TS to provide the peak level value. 7.19 address mode the address mode is used to select a device for subsequent data transfer and to define the destination registers. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 data bits. the fundamental timing is shown in fig.5. data bits 7 to 2 represent a 6-bi t device address, with bit 7 being the msb and bit 2 the lsb. the address of the UDA1341TS is 000101. data bits 0 to 1 indicate the type of the subsequent data transfer as shown in table 4. in the event that the UDA1341TS receives a different address, it will dese lect its microcontro ller interface logic. 7.20 data transfer mode the selection activated in the address mode remains active during subsequent da ta transfers, until the UDA1341TS receives a new address command. the fundamental timing of data transfers is essentially the same as the timing in the address mode and is given in fig.6. note that ?l3data write? denotes data transfer from the microcontroller to the UDA1341TS and ?l3data peak read? denotes data transfer in the opposite direction. the maximum input clock and data rate is 64f s . all transfers are byte-wise, i.e. they are based on groups of 8 bits. data will be stored in the UDA1341TS after the eighth bit of a byte has been received. a multibyte transfer is illustrated in fig.7.
2002 may 16 12 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS table 4 selection of data transfer bit 1 bit 0 mode transfer 0 0 data0 direct addressing registers: volume, bass boost, treble, peak detection position, de-emphasis, mute and mode extended addressing registers: digital mixer co ntrol, agc control, mi c sensitivity control, input gain, agc time constant and agc output level 0 1 data1 peak level value read-out (information from UDA1341TS to microcontroller) 1 0 status reset, system clock frequenc y, data input format, dc-filter, input gain switch , output gain switch, polarity control, double speed and power control 1 1 not used fig.5 timing address mode. handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgr431 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a
2002 may 16 13 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS fig.6 timing for data transfer mode. handbook, full pagewidth t stp(l3) t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mgr430 pl0 pl5 pl4 pl3 pl2 pl1 t clk(l3)h t clk(l3)l fig.7 multibyte transfer. handbook, full pagewidth t stp(l3) address l3data l3clock l3mode address data byte #1 data byte #2 mgr432
2002 may 16 14 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21 programming the sound processing and other features the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data type that is transferred. this is performed in the address mode using bit 0 and bit 1 (see table 4). the second selection is performed by the 2 or 3 msbs of the data byte (bits 7 and 6 or bits 7, 6 and 5). the other bits in the data byte (bits 5 to 0 or bits 4 to 0) represent the value that is placed in the selected registers. for the UDA1341TS the following modes can be selected: ? status in this mode the features re set, system clock frequency, data input format, dc-filter , input gain switch, output gain switch, polarity control, double speed and power control can be controlled. ? data0 there are two addressing modes: direct addressing mode and extended addressing mode. direct addressing mode is using the 2 msb bits of the data byte. via this addressing mode the features volume, bass boost, treble, peak position, de-emphasis, mute, and mode can be controlled directly. extended addressing mode is provid ed for controlling the features digital mixer, ag c control, mic sensitivity, input gain, agc time constant s, and agc output level. an extended address can be set via the ea registers (3 bits). the data in the extended registers can be set by writing data to the ed registers (5 bits). ? data1 in this mode the detected peak level value can be read out. table 5 default settings symbol feature setting or value status ogs output gain switch 0 db igs input gain switch 0 db pad polarity of adc non-inverting pda polarity of dac non-inverting ds double speed single speed pc power control adc and dac on direct control vc volume control 0 db bb bass boost 0 db tr treble 0 db pp peak detection position after the tone features de de-emphasis no de-emphasis mt mute no mute m mode switch flat extended programming ma mixer gain channel 1 ? 6db mb mixer gain channel 2 ? 6db ms mic sensitivity 0 db mm mixer mode switch double differential ag agc control disable agc at agc attack and decay time 11 ms and100 ms al agc output level ? 9dbfs
2002 may 16 15 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.1 status control table 6 data transfer of type ?status? bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register selected 0 rst sc1 sc0 if2 if1 if0 dc rst = reset sc = system clock frequency (2 bits) if = data input format (3 bits) dc = dc-filter 1 ogs igs pad pda ds pc1 pc0 ogs = output gain (6 db) switch igs = input gain (6 db) switch pad = polarity of adc pda = polarity of dac ds = double speed pc = power control (2 bits) 7.21.1.1 reset a 1-bit value to initialize the l3-registers with the default settings except system clock frequency. table 7 reset settings 7.21.1.2 system clock frequency a 2-bit value to select the used external clock frequency. table 8 system clock settings 7.21.1.3 dc-filter a 1-bit value to enable the digital dc-filter. table 9 dc-filtering settings 7.21.1.4 data input format a 3-bit value to select the data input format. table 10 data input format settings rst function 0no reset 1 reset sc1 sc0 function 0 0 512f s 0 1 384f s 1 0 256f s 1 1 not used dc function 0 no dc-filtering 1 dc-filtering if2 if1 if0 function 000i 2 s-bus 0 0 1 lsb-justified 16 bits 0 1 0 lsb-justified 18 bits 0 1 1 lsb-justified 20 bits 1 0 0 msb-justified 1 0 1 lsb-justified 16 bits input and msb-justified output 1 1 0 lsb-justified 18 bits input and msb-justified output 1 1 1 lsb-justified 20 bits input and msb-justified output
2002 may 16 16 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.1.5 output gain switch a 1-bit value to control the dac output gain switch. the default setting is given in table 5. table 11 gain switch of dac settings 7.21.1.6 input gain switch a 1-bit value to control the adc input gain switch. the default setting is given in table 5. table 12 gain switch of adc settings 7.21.1.7 polarity of adc a 1-bit value to control the adc polarity. the default setting is given in table 5. table 13 polarity control of adc settings 7.21.1.8 polarity of dac a 1-bit value to control the dac polarity. the default setting is given in table 5. table 14 polarity control of dac settings 7.21.1.9 double speed a 1-bit value to enable the double speed playback. the default setting is given in table 5. table 15 double speed settings 7.21.1.10 power control a 2-bit value to disable the adc and/or dac to reduce power consumption. the default setting is given in table 5. table 16 power control settings ogs gain of dac 00db 16db igs gain of adc 00db 16db pad polarity of adc 0 non-inverting 1 inverting pda polarity of dac 0 non-inverting 1 inverting ds function 0 single speed playback 1 double speed playback pc1 pc0 function adc dac 00 off off 01 off on 1 0 on off 11 on on
2002 may 16 17 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.2 data0 direct control table 17 data transfer of type ?data0? bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register selected 0 0 vc5 vc4 vc3 vc2 vc1 vc0 vc = volume control (6 bits) 0 1 bb3 bb2 bb1 bb0 tr1 tr0 bb = bass boost (4 bits) tr = treble (2 bits) 1 0 pp de1 de0 mt m1 m0 pp = peak detection position de = de-emphasis (2 bits) mt = mute m = mode switch (2 bits) 1 1 0 0 0 ea2 ea1 ea0 ea = extended address (3 bits) 1 1 1 ed4 ed3 ed2 ed1 ed0 ed = extended data (5 bits) 7.21.2.1 volume control a 6-bit value to program the left and right channel volume attenuation. the range is from 0 to ? db in steps of 1 db. the default setting is given in table 5. table 18 volume settings 7.21.2.2 bass boost a 4-bit value to program the bass boost settings. the used set depends on the mode bits. the default setting is given in table 5. table 19 bass boost settings vc5vc4vc3vc2vc1vc0 volume (db) 000000 0 000001 0 000010 ? 1 000011 ? 2 :::::: : 111011 ? 58 111100 ? 59 111101 ? 60 111110 ? 111111 ? bb3 bb2 bb1 bb0 bass boost flat (db) min. (db) max. (db) 0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 10 10 0110 0 12 12 0111 0 14 14 1000 0 16 16 1001 0 18 18 1010 0 18 20 1011 0 18 22 1100 0 18 24 1101 0 18 24 1110 0 18 24
2002 may 16 18 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.2.3 treble a 2-bit value to program the treble setting. the used set depends on the mode bits. the default setting is given in table 5. table 20 treble settings 7.21.2.4 peak detection position a 1-bit value to control the position of the peak level detector in the signal processing path. the default setting is given in table 5. table 21 peak detection position settings 7.21.2.5 de-emphasis a 2-bit value to enable the digital de-emphasis filter. the default setting is given in table 5. table 22 de-emphasis settings 7.21.2.6 mute a 1-bit value to enable the digital mute. the default setting is given in table 5. table 23 mute settings 7.21.2.7 mode a 2-bit value to program the mode of the sound processing filters of bass boost and treble. the default setting is given in table 5. table 24 mode filter switch settings tr1 tr0 treble flat (db) min. (db) max. (db) 00 0 0 0 01 0 2 2 10 0 4 4 11 0 6 6 pp function 0 before tone features 1 after tone features de1 de0 function 0 0 no de-emphasis 0 1 de-emphasis: 32 khz 1 0 de-emphasis: 44.1 khz 1 1 de-emphasis: 48 khz mt function 0no mute 1mute m1 m0 function 00flat 0 1 minimum 1 0 minimum 1 1 maximum
2002 may 16 19 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.3 data0 extended programming registers table 25 extended control registers ea2 ea1 ea0 ed4 ed3 ed2 ed1 ed0 register selected 0 0 0 ma4 ma3 ma2 ma1 ma0 ma = mixer gain channel 1 (5 bits) 0 0 1 mb4 mb3 mb2 mb1 mb0 mb = mixer gain channel 2 (5 bits) 0 1 0 ms2 ms1 ms0 mm1 mm0 ms = mic sensitivity (3 bits) mm = mixer mode (2 bits) 100ag00ig1ig0ag=agc control ig = input amplifier gain channel 2 (2 bits) 1 0 1 ig6 ig5 ig4 ig3 ig2 ig = input amplifier gain channel 2 (5 bits) 1 1 0 at2 at1 at0 al1 al0 at = agc time constant (3 bits) al = agc output level (2 bits) programming via extended addressing is done by first sending a data0 data byte ea (3 bits) which specifies the addresses of the extended register followed by a data0 data byte which specifies the contents of the extended data register (5 bits). the ea extended addresses and names of the extended data registers are given in table 25. 7.21.3.1 mixer gain control two 5-bit values to program the channel 1 (ma) and channel 2 (mb) coefficients in the mixer mode. the range is from 0 to ? db in steps of 1.5 db. the default settings are given in table 5. table 26 mixer gain control channel 1 and channel 2 settings 7.21.3.2 mic sensitivity a 3-bit value to program eight gain settings of the microphone amplifier. these settings are valid only when agc control is enabled and not in the double differential mode. the default setting is given in table 5. table 27 mic sensitivity settings ma4 mb4 ma3 mb3 ma2 mb2 ma1 mb1 ma0 mb0 mixer gain (db) 00000 0 00001 ? 1.5 00010 ? 3.0 ::::: : 11101 ? 43.5 11110 ? 45.0 11111 ? ms2 ms1 ms0 mic amplifier gain (db) 000 ? 3 001 0 010 +3 011 +9 100 +15 101 +21 110 +27 1 1 1 not used
2002 may 16 20 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.3.3 mixer mode a 2-bit value to program the mode of the digital mixer. there are four modes: double differential, input channel 1 select, input channel 2 select and digital mixer mode. the default setting is given in table 5. table 28 mixer mode switch settings 7.21.3.4 agc control a 1-bit value to enable the agc input. the default setting is given in table 5. table 29 agc control settings 7.21.3.5 agc output level a 2-bit value to program the agc output level. the default setting is given in table 5. table 30 agc output level settings 7.21.3.6 input channel 2 amplifier gain a 7-bit value to program the input channel 2 amplifier gain. the range is from ? 3 to +60.5 db in steps of 0.5 db. these settings are only valid when agc control is disabled and not valid in the double differential mode. table 31 input channel 2 amplifier gain settings 7.21.3.7 agc time constant a 3-bit value to program the attack and the decay parameters of the digital agc. the default setting is given in table 5. table 32 agc time constant settings mm1 mm0 function 0 0 double differential mode 0 1 input channel 1 select (input channel 2 off) 1 0 input channel 2 select (input channel 1 off) 1 1 digital mixer mode (input 1 ma + input 2 mb) ag function 0 disable agc: manual gain setting through ig (7 bits) 1 enable agc: gain control with manual mic sensitivity setting al1 al0 output level (db fs) 00 ? 9.0 01 ? 11.5 10 ? 15.0 11 ? 17.5 ig6 ig5 ig4 ig3 ig2 ig1 ig0 input channel 2 amplifier gain (db) 0000000 ? 3.0 0000001 ? 2.5 0000010 ? 2.0 0000011 ? 1.5 0000100 ? 1.0 0000101 ? 0.5 0000110 0.0 ::::::: : 1111101 59.5 1111110 60.0 1111111 60.5 at2 at1 at0 attack time (ms) decay time (ms) 000 11 100 001 16 100 010 11 200 011 16 200 100 21 200 101 11 400 110 16 400 111 21 400
2002 may 16 21 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 7.21.4 data1 control table 33 data transfer of type ?data1? 7.21.4.1 peak level value a 6-bit value to indicate the peak level value of the playback data. the largest value of the left and right channel data in the playback signal path is held since the last read-out of the microcontroller. table 34 peak level read-out data notes 1. peak value (db) = (peak level ? 63.5) 5 log 2. 2. for peak data >010011, the error in the peak value is 3. for peak data <010100, the error is larger due to limited bit length. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read-out data pl5 pl4 pl3 pl2 pl1 pl0 peak level value (6 bits) pl5 pl4 pl3 pl2 pl1 pl0 peak value (1) (db) 000000 ? 000001n.a. 000010n.a. 000011 ? 90.31 000100n.a. 000101n.a. 000110n.a. 000111 ? 84.29 ::::::: 010011note2 010100note3 ::::::: 111101 ? 2.87 111110 ? 1.48 1111110.00 < 11 2 log 4 --------------------------
2002 may 16 22 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 8 limiting values in accordance with the absolute maximum rating system (iec 60134); v ddd =v dda = 3 v; all voltages measured with respect to ground; t amb =25 c; unless otherwise specified. notes 1. all v dd and v ss connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k series resistor. 3. equivalent to discharging a 200 pf capacitor via a 2.5 h series inductor. 4. dac operation cannot be guaranteed after a short-circuit has occurred. 9 thermal characteristics 10 dc characteristics v ddd =v dda =3v; t amb =25 c; r l =5k ; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. symbol parameter conditions min. max. unit v dd supply voltage note 1 ? 5.0 v t xtal(max) maximum crysta l temperature ? 150 c t stg storage temperature ? 65 +125 c t amb operating ambient temperature ? 20 +85 c v es electrostatic handling note 2 ? 2000 +2000 v note 3 ? 250 +250 v i lu(prot) latch-up protection current t amb =125 c; v dd = 3.6 v ? 200 ma i sc(dac) dac short-circuit current: t amb =0 c; v dd = 3.0 v; note 4 output short-ci rcuited to v ssa(dac) ? 482 ma output short-ci rcuited to v dda(dac) ? 346 ma symbol parameter conditions value unit r th(j-a) thermal resistance from juncti on to ambient in free air 90 k/w symbol parameter conditions min. typ. max. unit supplies v dda(adc) adc analog supply voltage note 1 2.4 3.0 3.6 v v dda(dac) dac analog supply voltage note 1 2.4 3.0 3.6 v v ddd digital supply voltage note 1 2.4 3.0 3.6 v i dda(adc) adc analog supply current operation mode ? 12.5 ? ma adc power-down ? 6.0 ? ma i dda(dac) dac analog supply current operation mode ? 7.0 ? ma dac power-down ? 50 ? a i ddd digital supply current operation mode ? 7.0 ? ma dac power-down ? 4.0 ? ma adc power-down ? 3.0 ? ma
2002 may 16 23 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS notes 1. all power supply pins (v dd and v ss ) must be connected to the same external power supply unit. 2. when higher capacitive loads (above 50 pf) must be driven then a resistor of 100 must be connected in series with the dac output in order to prevent oscillations in the output operational amplifier. digital input pins v ih high-level input voltage 0.8v ddd ? v ddd +0.5 v v il low-level input voltage ? 0.5 ? 0.2v ddd v |i li | input leakage current ?? 10 a c i input capacitance ?? 10 pf digital output pins v oh high-level output voltage i oh = ? 2ma 0.85v ddd ?? v v ol low-level output voltage i ol =2ma ?? 0.4 v analog-to-digital converter v adcp positive reference voltage ? v dda ? v v adcn negative reference voltage 0.0 0.0 0.0 v r o(ref) v ref reference output resistance pin 28 ? 24 ? k r i input resistance measured at 1 khz stand-alone mode ? 12.5 ? k double differential mode ? 6.25 ? k c i input capacitance ? 20 ? pf programmable gain amplifier (input channel 2) r i input resistance microphone mode ? 12.5 ? k double differential mode ? >1 ? m digital-to-analog converter r o output resistance ? 0.13 3.0 i o(max) maximum output curr ent (thd + n)/s < 0.1% ? 0.22 ? ma r l load resistance 3 ?? k c l load capacitance note 2 ?? 50 pf reference voltage v ref reference voltage with respect to v ssa 0.45v dda 0.5v dda 0.55v dda v symbol parameter conditions min. typ. max. unit
2002 may 16 24 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 11 ac characteristics (analog) v ddd =v dda =3v; f i = 1 khz; f s =44.1khz; t amb =25 c; r l =5k ; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified . symbol parameter conditions min. typ. max. unit analog-to-digital converter v i(rms) input voltage (rms value) notes 1 and 2 ? 1.0 ? v v i unbalance between channels ? 0.1 ? db (thd + n)/s total harmonic distortion-plus-noise to signal ratio stand-alone mode 0db ?? 85 ? 80 db ? 60 db; a-weighted ?? 37 ? 33 db double differential mode 0db ?? 90 ? 85 db ? 60 db; a-weighted ?? 40 ? 36 db s/n signal-to-noise ratio v i = 0 v; a-weighted stand-alone mode ? 97 ? db double differential mode ? 100 ? db cs channel separation ? 100 ? db psrr power supply rejection ratio f ripple =1khz; v ripple(p-p) =30mv ? 30 ? db manual gain mode (agc disabled) g min minimum gain ?? 3 ? db g max maximum gain ? 60.5 ? db g step digital gain step ? 0.5 ? db programmable gain amplifier v i(rms) input voltage (rms value) at full-scale ? 3 db setting ? 1414 ? mv 0db setting ? 1000 ? mv 3db setting ? 708 ? mv 9db setting ? 355 ? mv 15 db setting ? 178 ? mv 21 db setting ? 89 ? mv 27 db setting ? 44 ? mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio at 0 db ? 3 db setting ?? 75 ? db 0db setting ?? 85 ? db 3db setting ?? 85 ? db 9db setting ?? 85 ? db 15 db setting ?? 80 ? db 21 db setting ?? 75 ? db 27 db setting ?? 75 ? db
2002 may 16 25 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS notes 1. the adc inputs can be used in a 2 v (rms value) input signal configuration when a resistor of 12 k is used in series with the inputs and 1 or 2 v (rms value) input signal operation can be selected via the input gain switch (igs). 2. the adc input signal scales inversely proportional with the power supply voltage. 3. the dac output voltage scales linear with the dac analog supply voltage. (thd + n)/s total harmonic distortion-plus-noise to signal ratio at ? 60 db; a-weighted ? 3 db setting ? tbf ? db 0db setting ?? 37 ? db 3db setting ? tbf ? db 9db setting ? tbf ? db 15 db setting ? tbf ? db 27 db setting ? tbf ? db digital-to-analog converter v o(rms) output voltage (rms value) note 3 ? 900 ? mv v o unbalance between channels ? 0.1 ? db (thd + n)/s total harmonic distortion-plus-noise to signal ratio 0db ?? 91 ? 86 db ? 60 db; a-weighted ?? 40 ? db s/n signal-to-noise ratio code = 0; a-weighted ? 100 ? db cs channel separation ? 100 ? db psrr power supply rejection ratio f ripple =1khz; v ripple(p-p) =100mv ? 50 ? db symbol parameter conditions min. typ. max. unit
2002 may 16 26 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 12 ac characteristics (digital) v ddd =v dda = 2.7 to 3.6 v; t amb = ? 20 to +85 c; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. symbol parameter conditions min. typ. max. unit system clock timing (see fig.8) t sys clock cycle time f sys =256f s 78 88 131 ns f sys =384f s 52 59 87 ns f sys =512f s 39 44 66 ns t cwl low-level pulse width f sys < 19.2 mhz 0.30t sys ? 0.70t sys ns f sys 19.2 mhz 0.40t sys ? 0.60t sys ns t cwh high-level pulse width f sys < 19.2 mhz 0.30t sys ? 0.70t sys ns f sys 19.2 mhz 0.40t sys ? 0.60t sys ns serial input/output data timing (see fig.9) t cy bit clock cycle time 300 ?? ns t bck(h) bit clock high time 100 ?? ns t bck(l) bit clock low time 100 ?? ns t r rise time ?? 20 ns t f fall time ?? 20 ns t s;dati data input set-up time 20 ?? ns t h;dati data input hold time 0 ?? ns t d;dato(bck) data output delay time (from bck falling edge) ?? 80 ns t d;dato(ws) data output delay time (from ws edge) msb-justified format ?? 80 ns t h;dato data output hold time 0 ?? ns t s;ws word select set-up time 20 ?? ns t h;ws word select hold time 10 ?? ns microcontroller l3 -interface timing (see figs 5 and 6) t cy(clk)(l3) l3clock 500 ?? ns t clk(l3)h l3clock high time 250 ?? ns t clk(l3)l l3clock low time 250 ?? ns t su(l3)a l3mode set-up time addressing mode 190 ?? ns t h(l3)a l3mode hold time addressing mode 190 ?? ns t su(l3)d l3mode set-up time data transfer mode 190 ?? ns t h(l3)d l3mode hold time data transfer mode 190 ?? ns t su(l3)da l3data set-up time data transfer and addressing mode 190 ?? ns t h(l3)da l3data hold time data transfer and addressing mode 30 ?? ns t stp(l3) l3mode halt time 190 ?? ns
2002 may 16 27 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS fig.8 system clock timing. handbook, full pagewidth mgl443 t cwh t cwl t sys fig.9 serial interface timing. handbook, full pagewidth mgg840 ws bck datao datai t f t r t h;ws t s;ws t bck(h) t bck(l) t cy t h;dato t s;dati t h;dati t d(dato)(bck) t d(dato)(ws)
2002 may 16 28 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 13 application information fig.10 application diagram. handbook, full pagewidth mgr433 47 r30 c11 100 f (16 v) c12 100 f (16 v) v dda v ddd l1 blm32a07 blm32a07 l2 + 3 v ground 1 v ssa(adc) UDA1341TS 12 28 sysclk v ref 10 35711 v ddd v dda(adc) v adcn v adcp v ssd system clock 18 datao 16 bck 17 ws overflow flag 9 overfl c1 47 f (16 v) 2 vinl1 26 voutl r23 100 r22 10 k 24 voutr r26 100 r27 10 k c4 47 f (16 v) 4 vinr1 19 datai 13 l3mode 14 l3clock 15 l3data 100 nf (63 v) r21 1 c2 100 f (16 v) c25 100 nf (63 v) c21 v dda c3 47 f (16 v) c8 47 f (16 v) c5 47 f (16 v) c22 100 nf (63 v) 23 qmute 22 agcstat 21 test2 20 test1 100 nf (63 v) r28 1 c9 100 f (16 v) c29 v ddd v dda(dac) v ssa(dac) 25 27 r29 1 c10 100 f (16 v) c27 100 nf (63 v) v dda left output right output left line input right c6 47 f (16 v) 6 vinl2 c7 47 f (16 v) 8 vinr2 left mic input right
2002 may 16 29 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 14 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale s sop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341 -1 a max. 2
2002 may 16 30 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ?data handbook ic26; integrated circuit packages? (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering ca n still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 15.2 reflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215to250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specif ically developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): ? larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; ? smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will elim inate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limit ed to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 may 16 31 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 15.5 suitability of surface m ount ic packages for wave and reflow soldering methods notes 1. for more detailed information on the bga packages refer to the ?(lf)bga application note ? (an01026); order a copy from your nxp semicond uctors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the ?data handbook ic26; integrated circuit packages; section: packing methods? . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 may 16 32 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS 16 data sheet status notes 1. please consult the most recently issued document before initiating or completing a design. 2. the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. the latest pr oduct status information is available on the internet at url http://www.nxp.com. document status (1) product status (2) definition objective data sheet development this document contains data from the objective specification for product development. preliminary data sheet qualification this document contains data from the preliminary specification. product data sheet production this document contains the product specification. 17 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semico nductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without lim itation - lost profits, lost savings, business interrup tion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semi conductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, lif e-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for incl usion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are fo r illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assi stance with ap plications or customer product design. it is customer?s sole responsibility to dete rmine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as for the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applications and products using nxp semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect.
2002 may 16 33 nxp semico nductors product specification economy audio codec for minidisc (md) home stereo and port able applications UDA1341TS limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will c ause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeat ed exposure to lim iting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the general terms and conditions of comme rcial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconductors products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. quick reference data ? the quick refere nce data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semiconductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semicond uctors? warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond nxp semiconductors? standard warranty and nxp semiconductors? product specifications.
nxp semiconductors provides high performance mixed signal and standard product solutions that leverage its leadi ng rf, analog, power management, interface, security and digital processing expertise contact information for additional information please visit: http://www.nxp.com for sales offices addresses send e-mail to: salesaddresses@nxp.com ? nxp b.v. 2010 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liabilit y will be accepted by the publisher for any consequen ce of its use. publicat ion thereof d oes not con vey nor imply any license under patent- or other industrial or intellectual property rights. customer notification this data sheet was changed to reflect the new company name nxp semiconductors, including new legal definitions and disclaimers. no changes were made to the technical content, except for package outline drawings which were updated to the latest version. printed in the netherlands 753505/04/pp 34 date of release: 2002 may 16 document order number: 9397 750 09805

▲Up To Search▲

Price & Availability of UDA1341TS

	To Download UDA1341TS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .